Cadence Announces DDR4 and LPDDR4 IP Achieve 3,200 Mbit/s on TSMC 16 nm FinFET Plus Process
SAN JOSE, Calif., March 14, 2016 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its DDR4 and LPDDR4 IP products for TSMC’s 16 nm FinFET Plus (16 FF+) process have completed TSMC9000 Silicon Assessment. The Cadence® Denali® DDR controller IP, and both the Denali DDR4 and LPDDR4 PHY IP, have demonstrated operating speeds of up to 3,200 Mbit/s, and each are in production with several customers. Memory interface performance is crucial for alleviating the key system bottleneck of memory access, which can overshadow increases in processor performance. The high performance of Cadence’s Denali DDR interface solutions supports the demanding data bandwidth requirements of various applications, including mobile, cloud computing, and networking.
Huawei Announces Breakthrough in All-Optical Cross-Connect Field
ANAHEIM, Calif., March 23, 2016 — Huawei, a leading global Information and Communications Technology (ICT) solutions provider, has today announced that it is releasing ultra-large port non-blocking wavelength adding/dropping technology (also known as ADWSS) and corresponding optical node architecture.
The announcement was made at the Optical Fiber Communication Conference and Exhibition (OFC) 2016, the largest such global conference and exposition. Huawei also showcased an 8-degree ADWSS prototype that supports wavelength adding and dropping on 128 ports, implementing the free optical cross-connection of 640 wave-lengths on these ports. This is a technical breakthrough in the all-optical cross-connect field and achieves dramatic progress in developing all-optical cross-connections on transport networks.
IBM and the University of Illinois to Pioneer Next-Generation Cognitive Computing Systems
YORKTOWN HEIGHTS, N.Y. and URBANA, Ill., April 15, 2016 — IBM Research (NYSE: IBM) today announced plans for a multi-year collaboration with the University of Illinois Urbana-Champaign to create the Center for Cognitive Computing Systems Research (C3SR), which will be housed within the College of Engineering on the Urbana campus. Opening in the summer of 2016, the C3SR will integrate and advance scientific frontiers in both machine learning and heterogeneous computing systems optimized for new cognitive computing workloads.
Chain and Global Financial Firms Unveil Open Standard for Blockchain
SAN FRANCISCO, May 2, 2016 — Chain, Inc., a leading provider of blockchain technology, today announced the public release of Chain Open Standard 1 (Chain OS 1), an open source blockchain protocol developed over the last 18 months through a unique collaboration between the Silicon Valley company and global financial services firms.
The Chain Open Standard is already powering several blockchain projects at leading financial companies, which drove the requirements for the standard through deep partnerships with Chain that began as far back as 2014. The standard is being opened up to the wider financial community for the first time today.
Latest Synopsys IC Compiler II Release Boosts Quality-of-Results for Performance-Critical Designs
MOUNTAIN VIEW, Calif., May 17, 2016 — Synopsys, Inc. (NASDAQ: SNPS) today announced the immediate availability of the 2016.03 release of its IC Compiler™ II place-and-route solution, further bolstering its leadership in Quality-of-Results (QoR) across a diverse application base. Excellent Turnaround Time (TAT) coupled with achieved-QoR has led customers like HiSilicon and Movidius to select IC Compiler II as their primary implementation tool for their next-generation performance-critical designs.
This latest production release raises the bar on achievable QoR through the deployment of new technologies, including congestion-driven restructuring, power-aware concurrent-clock-and-data optimizations, advanced full-flow power optimization, and improvements in route-guided design closure. The combination of these capabilities delivers up to 15 percent area, timing, and power improvements, enabling the highest levels in performance. With this release of IC Compiler II, Synopsys continues to strengthen its deployment momentum across the broad design community.
- Technology advancements in the latest release deliver exceptional QoR across all key metrics: Up to 5 percent smaller area, 10 percent lower power, and 5 percent better timing.
- 10x faster design planning, 5x faster implementation and 2x more capacity continues to reshape the physical design landscape.
- Driven by transformational benefits observed, HiSilicon and Movidius have standardized on IC Compiler II as their physical design platform for next-generation SoCs.
IDT’s FemtoClock Family Delivers Unparalleled Frequency Flexibility for Complex Timing Networks
SAN JOSE, Calif., May 18, 2016 — Integrated Device Technology, Inc. (IDT) (NASDAQ: IDTI) today introduced a uniquely flexible frequency synthesizer that hands the system designer options to pre-configure the settings of the device or program them in the system, or a combination of both. With an industry-first eight fractional and two integer output dividers, the IDT® 8T49N1012 FemtoClock® NG synthesizer delivers a single-chip solution that aids design engineers in resolving complex timing requirements while hitting important performance parameters.
Lattice Engines Announces Next-Generation Predictive Insight Platform
SAN MATEO, Calif., May 24, 2016 — Lattice Engines, the largest and fastest growing provider of predictive marketing and sales applications to the enterprise, launched the Lattice Predictive Insight Platform today. It is the only enterprise-grade marketing platform that features real-time contact and account scoring, rapid self-service modeling, and native applications for Marketo, Eloqua, and Salesforce.
With the release of this new predictive platform, marketing teams of any skill level can easily create predictive segments and models based on data for both traditional and Account-Based Marketing (ABM) programs. Once deployed, the scoring of contacts and accounts occurs within seconds so marketing and sales teams can take immediate action. Sales reps are provided unprecedented insight into every Lattice-scored account, including firmographic, technographic, intent, and engagement data.
Microsoft and Facebook to build a new subsea cable across the Atlantic Ocean
MENLO PARK, Calif. and REDMOND, Wash., May 26, 2016 — Microsoft and Facebook announced an agreement to build a new, state-of-the-art subsea cable across the Atlantic. The new ‘MAREA’ cable will help meet the growing customer demand for high speed, reliable connections for cloud and online services for Microsoft, Facebook, and their customers. The parties have cleared conditions to go Contract-In-Force (CIF) with their plans, and construction of the cable will commence in August 2016 with completion expected in October 2017.
Microsoft and Facebook are collaborating on this system to accelerate the development of the next-generation of Internet infrastructure and support the explosion of data consumption and rapid growth of their respective cloud and online services. MAREA will be the highest-capacity subsea cable to ever cross the Atlantic — eight fiber pairs and an initial estimated design capacity of 160 Tbit/s. The new 6,600 km submarine cable system (to be operated and managed by Telxius, Telefónica’s new telecommunications infrastructure company) will also be the first to connect the U.S. to southern Europe from the data hub in northern Virginia to Bilbao, Spain and then to network hubs in Europe, Africa, the Middle East, and Asia. This route is south of other transatlantic cable systems, thereby helping ensure more resilient and reliable connections for customers in the United States, Europe, and beyond.
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